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Netlist extract and vias

PostPosted: Sat Mar 02, 2013 2:39 pm
by marius
The newer versions of CAMMaster will assign midpoint status to vias differently than previous versions.
We refer here to holes that connect two plane circuits from different layers.
Some of these holes need to be tested and some don't. This will be reflected in the netlist files output by whether the points will be endpoints or midpoints.

First, note that there is a very useful midpoint inspection tool in CAMMaster. This is useful after extracting a netlist.
Snap1.png


After activating this tool one can click over a padstack and see the midpoint / endpoint state of all in the status line:

Snap2.png


For drill holes that you don't want tested and that go through plane areas, make sure that there are no covering pads on either the CPU or CPL layers.
These pads will be invisible because the will are covered by the plane (either a polygon or a fill with traces).

To delete these pads, use the "Select by intersection" tool.
This is a very powerful tool and once you learn how to use it, it is not difficult to use.

To delete covering pads on CPU (same can be done on CPL).

(1) FIrst select only pads in CPU
Snap3.png


(2) Then add to this selection all of one of the internal plane layers (one that has matching circuit area for the plane circuitry)
Snap4.png


(3) Now run the "Select by intersection" like this:
Snap5.png

snap6.png

where the "Destination layer" is CPU and the "Reference layer" is the plane layer.

(4) Pads will be selected and can be deleted
snap7.png


If one runs the netlist extract now, the holes that were covered by these pads whill have midpoint status and they will not be tested on the tester side.